The present invention relates to a circuit arrangement for synchronizing a local sampling clock to the frame position and the phase of the characters of a received character stream containing a unique word at regular time intervals, wherein a digital correlator generates a crosscorrelation function from the received character stream, sampled at the sampling clock rate, and a unique word stored at the receiving end, and wherein a frame detection circuit derives a first frame clock from those maxima of the crosscorrelation function recurring at intervals of one frame period.
In such a circuit arrangement, the frame clock is recovered from a "unique word" by using digital correlation techniques, whereas the bit clock is recovered, in a manner not described, from an additional bit pattern preceding the unique word (IEEE Transactions on Communication Technology, Vol. COM-16, No. 4, August 1968, pp. 597 to 605). This circuit arrangement is intended for time-division multiple-access satellite communication systems, but the problem that the frame clock and the phase of the sampling clock must be synchronized to the received digital characters also arises in TDM wire communication systems for, e.g., two-wire full-duplex transmission over telephone subscriber lines. This is particularly difficult if the received digital characters are heavily distorted and cannot be equalized until after determination of the appropriate phase of the sampling clock.
A prior patent application (P No. 32 27 151.4) published on Feb. 2, 1984 has for its object to provide a circuit arrangement of the above kind which is also suitable for a heavily distorted received character stream. This object is attained by providing a phase synchronization circuit which derives control information for adjusting the phase of the sampling clock from values of the crosscorrelation function in the vicinity of each detected recurrent maximum, and adjusts the phase of the sampling clock with this control information. Furthermore, a clock-signal-synchronizing circuit has been provided in which the deviation of a characteristic, periodically recurring parameter of the received signal is measured at two different instants, and from the two measured values, the respective average of an error signal is determined. With this error signal, the clock phase is adjusted until the error signal disappears. As the characteristic parameter, the envelope of the received signal is used, for example (DE-OS No. 27 29 312). This clock synchronization, however, is designed specifically for data communication systems using phase-shift keying and requires quite a large amount of circuitry.
The clock recovery described in the prior application requires that the polarity of the received signal be known. However, this is not always insured because it is possible, for example, that the tip wire and the ring wire of the subscriber line are interchanged.